In electronics, a through silicon via (TSV) is a vertical electrical connection (via) passing completely through a silicon wafer or die. TSV technology is important in creating 3D packages and 3D integrated circuits. A 3D package (System in Package, Chip Stack MCM, etc.) contains two or more chips (integrated circuits) stacked vertically so that they occupy less space. An alternate type of 3D package can be where ICs are not stacked but a carrier substrate containing TSVs is used to connect multiple ICs together in a package. In most 3D packages, the stacked chips are wired together along their edges; this edge wiring slightly increases the length and width of the package and usually requires an extra “interposer” layer between the chips.
In some new 3D packages, TSVs replace edge wiring by creating vertical connections through the body of the chips. The resulting package has no added length or width. Because no interposer is required, a TSV 3D package can also be flatter than an edge-wired 3D package. This TSV technique is sometimes also referred to as TSS (Through-Silicon Stacking or Thru-Silicon Stacking). A 3D integrated circuit (3D IC) is a single integrated circuit built by stacking silicon wafers and/or dies and interconnecting them vertically so that they behave as a single device. By using TSV technology, 3D ICs can pack a great deal of functionality into a small “footprint.” In addition, critical electrical paths through the device can be drastically shortened, leading to faster operation.
In conventional semiconductor chips, ICs are formed along active surfaces of the semiconductor chips with conventional electrical terminals such as bonding pads formed on the active surface. In high-density electrical interconnections, 3D chip stacking was developed with electrical terminals not only disposed on the active surfaces but also on the corresponding back surfaces of the semiconductor chips. TSV is the enabled technology to vertically stack several chips to assemble 3D chip stacking packages or modules with high powers, high densities, and smaller dimensions. TSV's are electrically-conductive through holes inside a chip penetrating through the top surface and the bottom surface of a chip to create vertical electrical connections without any interposers nor bonding wires. TSV provides directly vertical electrical connections not go through the sidewalls at the edges of the chips to shorten the electrical paths. TSV technology can further enhance the integration and the performance of an electronic device to greatly reduce the packaging heights and dimensions, to increase the speeds, and to decrease the power consumption of an electronic device. However, each chip will generate heat during operation. Therefore, the induced thermal stresses will cause the chip to deform and even to break the electrical connections of TSV where stresses are concentrated.
U.S. Pat. No. 7,091,592 discloses a semiconductor chip. However, when the chip experiences thermal stresses causing deformation, the electrical connections formed by stud bumps located between the chips can be broken due to thermal stresses leading to electrical failure.
U.S. Pat. No. 7,838,967 discloses a semiconductor. However, the design proposed therein fails to maximize the full area of the semiconductor, or to account for failure of TSVs. As such, reliability remains a concern in U.S. Pat. No. 7,838,967.
U.S. Patent Application 20100182040 discloses programmable and non-programmable TSV in silicon chips. Metal/Insulator/Metal structures are used to switch programmable TSVs between open and shorted conditions while programming is conducted by complementary circuitry on two adjacent chips in a multi-story chip stack.
U.S. Patent Application 20100153043 discloses a TSV monitoring method through the use of inverters, connecting the inverters with the TSV circuit, enabling the circuit to oscillate, measuring the output signal on the inverter output, and determining the characteristics of TSVs based upon the output signal.
U.S. Patent Application 20100013512 discloses an electronic apparatus, systems, and methods to test and/or replace defective TSVs. Repeated measurement tests are conducted to infer an aging rate or failure rate.
U.S. Pat. No. 7,776,741 discloses a semiconductor electroplating process for depositing copper into through silicon via holes in a substantially void free filling.
U.S. Pat. No. 7,683,459 discloses a bonding method for TSV based wafer stacking. Patterned adhesive layers are utilized to join together wafers in the stack and solder bonding is used to electrically connect through the vias.
U.S. Pat. No. 7,670,950 discloses a method for metalizing a TSV feature in an IC device substrate. The method utilizes an electrolytic copper deposition immersion in a solution of copper ions and an organic sulfonic acid, or inorganic acid, or one or more organic compounds.
U.S. Pat. No. 7,564,115 discloses a TSV structure being tapered, with a hard mask region extending from the top surface, encircling a top portion of the TSV, dielectric layers over the substrate, and a metal post extending from the top surface of the dielectric layer to the TSV.
U.S. Patent Application 20100178766 discloses a high-yield method of exposing and contacting TSV structures. The electrical vias have conductive cores with surrounding insulator adjacent side and end regions of the cores.
U.S. Patent Application 20090319965 discloses a method and apparatus for thermal analysis of through-silicon via structures in an integrated circuit design layout. This invention is part of the larger IC design layout verification and qualification modeling that takes place before physical manufacturing.
U.S. Patent Application 20090267194 discloses a semiconductor chip. Higher production yields of TSV containing devices is the objective of this invention through the use of extruded rings features.
U.S. Patent Application 20100123241 discloses a semiconductor multi-chip packaging comprised of through-silicon via and a sidewall pad.
U.S. Patent Application 20090321939 discloses an integrated circuit bridge interconnect system with side-by-side die configurations that are electronically connected to each other by a bridge die with TSV connections from the bridge die to the first and second die in the side-by-side die configuration.
U.S. Patent Application 20090102021 discloses an integrated circuit structure with TSV structures with a TSV pad spaced apart from the TSV and a metal line over, and connecting, the TSV and the TSV pad.
U.S. Patent Application 20100187694 discloses a system and method for an improved through-silicon via structure. A low-K dielectric layer if formed on the sidewalls of the traditional vertical through silicon substrate via structure.
U.S. Patent Application 20100171223 discloses a TSV manufacturing process that creates TSVs with scalloped surface inner sidewalls. Additionally, the TSV structures may be sloped with either the circuit side or the backside openings having the larger via critical dimension.